? semiconductor components industries, llc, 2014 march, 2014 ? rev. 0 1 publication order number: NCP59749/d NCP59749 3.0 a, dual-rail very low\dropout linear regulator with programmable soft\start the NCP59749 is dual ? rail very low dropout voltage regulator that is capable of providing an output current in excess of 3.0 a with a dropout voltage of 120 mv typ. at full load current. the devices are stable with ceramic and any other type of output capacitor 2.2 f. this series contains adjustable output voltage version with output voltage down to 0.8 v . internal protection features consist of built ? in thermal shutdown and output current limiting protection. user ? programmable soft ? start and power good pins are available. the NCP59749 is available in qfn20 5x5 package. features ? output current in excess of 3.0 a ? v in range: 0.8 v to 5.5 v ? v bias range: 2.7 v to 5.5 v ? output voltage range: 0.8 v to 3.6 v ? dropout voltage: 120 mv at 3 a ? programmable soft start ? open drain power good output ? fast transient response ? stable with any type of output capacitor 2.2 f ? current limit and thermal shutdown protection ? these are pb ? free devices applications ? consumer and industrial equipment point of load regulation ? fpga, dsp and logic power supplies ? switching power supply post regulation figure 1. typical application schematic NCP59749 qfn20 case 485db marking diagram http://onsemi.com xxxxx = specific device code a = assembly location l/wl = wafer lot y/yy = year w/ww = work week = pb-free package (note: microdot may be in either location) pin connections see detailed ordering, marking and shipping information in the package dimensions section on page 9 of this data sheet. ordering information xxxxxxxx xxxxxxxx awlyyww qfn20 1 qfn20, 5x5, 0.65p in in in pg bias out out out nc fb in nc nc nc out en gnd nc nc ss gnd 20 19 18 17 16 15 14 13 12 11 1 2 3 4 5 6 7 8 9 10
NCP59749 http://onsemi.com 2 figure 2. simplified schematic block diagram table 1. pin function description name qfn ? 20 description in 5 ? 8 unregulated input to the device. en 11 enable pin. driving this pin high enables the regulator. driving this pin low puts the regulator into shutdown mode. this pin must not be left floating. ss 15 soft-start pin. a capacitor connected on this pin to ground sets the start-up time. if this pin is left floating, the regulator output soft-start ramp time is typically 200 s. bias 10 bias input voltage for error amplifier, reference, and internal control circuits. pg 9 power-good (pg) is an open-drain, active-high output that indicates the status of v out . when v out exceeds the pg trip threshold, the pg pin goes into a high-impedance state. when v out is below this threshold the pin is driven to a low-impedance state. a pull-up resistor from 10 k to 1 m should be connected from this pin to a supply up to 5.5 v. the supply can be higher than the input voltage. alternatively, the pg pin can be left floating if output monitoring is not necessary. fb 16 this pin is the feedback connection to the center tap of an external resistor divider network that sets the output voltage. this pin must not be left floating. out 1, 18 ? 20 regulated output voltage. a small capacitor (total typical capacitance 2.2 f, ceramic) is needed from this pin to ground to assure stability. nc 2 ? 4, 13, 14, 17 no connection. this pin can be left floating or connected to gnd to allow better thermal contact to the top-side plane. gnd 12 ground pad/tab should be soldered to the ground plane for increased thermal performance
NCP59749 http://onsemi.com 3 table 2. absolute maximum ratings parameter symbol value unit input voltage range v in ? 0.3 to +6 v input voltage range v bias ? 0.3 to +6 v enable voltage range v en ? 0.3 to +6 v power-good voltage range v pg ? 0.3 to +6 v pg sink current i pg 0 to +1.5 ma ss pin voltage range v ss ? 0.3 to +6 v feedback pin voltage range v fb ? 0.3 to +6 v output voltage range v out ? 0.3 to (v in + 0.3) 6 v maximum output current i out internally limited output short circuit duration indefinite continuous total power dissipation p d see thermal characteristics table and formula maximum junction temperature t jmax +125 c storage junction temperature range t stg ? 55 to +150 c esd capability, human body model (note 2) esd hbm 2000 v esd capability, machine model (note 2) esd mm 200 v stresses exceeding those listed in the maximum ratings table may damage the device. if any of these limits are exceeded, device function ality should not be assumed, damage may occur and reliability may be affected. 1. refer to electrical characteristics and application information for safe operating area. 2. this device series incorporates esd protection and is tested by the following methods: esd human body model tested per eia/jesd22-a114 esd machine model tested per eia/jesd22-a115 latch-up current maximum rating tested per jedec standard: jesd78. table 3. thermal characteristics rating symbol value unit thermal characteristics, qfn20, 5x5, 0.65p package thermal resistance, junction ? to ? ambient (note 5) r ja 30.5 c/w thermal resistance, junction ? to ? case (bottom) (note 6) r jc 4.1 c/w 3. refer to electrical characteristics and application information for safe operating area. 4. thermal data are derived by thermal simulations based on methodology specified in the jedec jesd51 series standards. the foll owing assumptions are used in the simulations: ? this data was generated with only a single device at the center of a high ? k (2s2p) board with 3 in x 3 in copper area which follows the ? jedec51.7 guidelines. ? the exposed pad is connected to the pcb ground layer through a 4x4 thermal via array. vias are 0.3 mm diameter, plated. ? each of top and bottom copper layers has a dedicated pattern for 20% copper coverage. 5. the junction ? to ? ambient thermal resistance under natural convection is obtained in a simulation on a high ? k board, following the jedec51.7 guidelines with assumptions as above, in an environment described in jesd51 ? 2a. 6. the junction ? to ? case (bottom) thermal resistance is obtained by simulating a cold plate test on the ic exposed pad. test description can be found in the ansi semi standard g30 ? 88. table 4. recommended operating conditions (note 7) rating symbol min max unit input voltage v in v out + v do 5.5 v bias voltage v bias 2.7 5.5 v junction temperature t j ? 40 125 c functional operation above the stresses listed in the recommended operating ranges is not implied. extended exposure to stresse s beyond the recommended operating ranges limits may affect device reliability. 7. refer to electrical characteristics and application information for safe operating area.
NCP59749 http://onsemi.com 4 table 5. electrical characteristics (at v en = 1.1 v, v in =v out + 0.3 v, c bias = 0.1 f, c ss = 1 nf, c in =c out =10 f, i out = 50 ma, v bias = 5.0 v, t j = ? 40 c to +125 c, unless otherwise noted. typical values are at t j = +25 c.) symbol parameter test conditions min typ max unit v in input voltage range v out +v do 5.5 v v bias bias pin voltage range 2.7 5.5 v uvlo undervoltage lock-out v bias rising hysteresis 1.2 1.6 0.4 1.9 v v ref internal reference (adj.) t j = +25 c 0.798 0.802 0.806 v v out output voltage range v in = 5 v, i out = 3.0 a v ref 3.6 v accuracy (note 1) v out + 2.2 v < v bias < 5.5 v, 50 ma < l out < 3.0 a - 2 0.5 + 2 % v out /v in line regulation v out (nom) + 0.3 < v in < 5.5 v 0.03 %/v v out /i out load regulation 50ma < i out < 3.0 a 0.09 %/a v do v in dropout voltage (note 2) i out = 3.0 a, v bias - v out (nom) 3.25 v (note 3) 120 280 mv v bias dropout voltage (note 2) i out = 3.0 a, v in = v bias 1.31 1.75 v i cl current limit v out = 80% x v out (nom) 3.8 4.6 6.0 a i bias bias pin current 1 2 ma i shdn shutdown supply current (i gnd ) v en 0.4 v 1 50 a i fb feedback pin current - 1 0.15 1 a psrr power-supply rejection (v in to v out ) 1 khz, i out = 1.5 a, v in = 1.8 v, v out = 1.5 v 60 db 300 khz, i out = 1.5 a, v in = 1.8 v, v out = 1.5 v 30 power-supply rejection (v bias to v out ) 1 khz, i out = 1.5 a, v in = 1.8 v, v out = 1.5 v 50 db 300 khz, i out = 1.5 a, v in = 1.8 v, v out = 1.5 v 30 noise output noise voltage 100 hz to 100 khz, l out = 3 a 25 x v out v rms t strt minimum startup time r load for i out = 1.0 a, c ss = open 200 s i ss soft-start charging current v ss = 0.4 v 0.44 a v en, hi enable input high level 1.1 5.5 v v en, lo enable input low level 0 0.4 v v en, hys enable pin hysteresis 50 mv v en, dg enable pin deglitch time 20 s i en enable pin current v en = 5 v 0.1 1 a v it pg trip threshold v out decreasing 85 90 94 %v out v hys pg trip hysteresis 3 %v out v pg, lo pg output low voltage i pg = 1 ma (sinking), v out < v it 0.3 v i pg, lkg pg leakage current v pg = 5.25 v, v out > v it 0.1 1 a tsd thermal shutdown temperature shutdown, temperature increasing reset, temperature decreasing +165 +140 c product parametric performance is indicated in the electrical characteristics for the listed test conditions, unless otherwise noted. product performance may not be indicated by the electrical characteristics if operated under different conditions. 1. adjustable devices tested at v ref ; external resistor tolerance is not taken into account. 2. dropout is defined as the voltage from the input to v out when v out is 3% below nominal. 3. 3.25 v is a test condition of this device and can be adjusted by referring to figure 8.
NCP59749 http://onsemi.com 5 typical characteristics at t j = +25 c, v in = v out(typ) + 0.3 v, v bias = 5 v, i out = 50 ma, v en = v in , c in = 1 f, c bias = 4.7 f, and c out = 10 f, unless otherwise noted. figure 3. v in line regulation figure 4. v bias line regulation v in ? v out (v) v bias ? v out (v) 4.5 4.0 3.0 2.0 1.5 1.0 0.5 0 ? 0.20 ? 0.15 ? 0.10 ? 0.05 0 0.10 0.15 0.20 3.5 3.0 4.0 2.5 2.0 1.5 1.0 0.5 ? 0.5 ? 0.4 ? 0.2 ? 0.1 0 0.2 0.4 0.5 figure 5. load regulation figure 6. load regulation i out , output current (ma) i out , output current (a) 50 40 30 20 10 0 ? 0.5 ? 0.4 ? 0.2 ? 0.1 0 0.2 0.3 0.5 1.5 1.0 0.5 0 ? 0.5 ? 0.4 ? 0.3 ? 0.1 0.1 0.2 0.4 0.5 figure 7. v in dropout voltage vs. i out and temperature t j figure 8. v in dropout voltage vs. (v bias ? v out ) and temperature t j i out , output current (a) v bias ? v out (v) 3.0 1.0 0.5 0 0 20 40 60 80 100 120 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 50 100 200 250 350 450 500 change in v out (%) change in v out (%) change in v out (%) change in v out (%) v do (v in ? v out ) dropout voltage (mv) 2.5 3.5 5.0 0.05 ? 0.3 0.1 0.3 +125 c +25 c ? 40 c +125 c +25 c ? 40 c ? 0.3 0.1 0.4 +125 c +25 c ? 40 c ? 0.2 0 0.3 +125 c +25 c ? 40 c +125 c +25 c ? 40 c 4.5 150 300 400 +125 c +25 c ? 40 c v do (v in ? v out ) dropout voltage (mv) 2.0 2.5 3.0 1.5 2.0 2.5 i out = 3 a
NCP59749 http://onsemi.com 6 typical characteristics at t j = +25 c, v in = v out(typ) + 0.3 v, v bias = 5 v, i out = 50 ma, v en = v in , c in = 1 f, c bias = 4.7 f, and c out = 10 f, unless otherwise noted. figure 9. v in dropout voltage vs. (v bias ? v out ) and temperature t j figure 10. v bias dropout voltage vs. i out and temperature t j v bias ? v out (v) i out , output current (a) 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 20 60 80 120 140 180 200 3.0 1.0 0.5 0 600 700 800 900 1000 1100 1400 figure 11. bias pin current vs. i out and temperature t j figure 12. bias pin current vs. v bias and temperature t j i out , output current (a) v bias (v) 3.0 1.0 0.5 0 0 200 600 800 1200 1400 1600 2000 5.0 4.5 4.0 5.5 3.5 3.0 2.5 2.0 0 200 600 800 1000 1400 1800 2000 figure 13. soft start charging current i ss vs. temperature t j figure 14. l ? level pg voltage vs. current t j , junction temperature ( c) i pg , pg pin current (ma) 100 75 125 50 25 0 ? 25 ? 50 0.300 0.325 0.350 0.375 0.400 0.450 0.475 0.500 12 10 8 6 4 2 0 0 0.1 0.3 0.4 0.5 0.7 0.9 1.0 v do (v in ? v out ) dropout voltage (mv) i bias ( a) i bias ( a) i ss ( a) v pg,lo , l ? level pg voltage (v) 4.5 +125 c +25 c ? 40 c i out = 0.5 a 40 100 160 v do (v bias ? v out ) dropout voltage (mv) +125 c +25 c ? 40 c 400 1000 1800 +125 c +25 c ? 40 c 400 1200 1600 +125 c +25 c ? 40 c 0.425 0.2 0.6 0.8 1.5 2.0 2.5 1200 1300 1.5 2.0 2.5
NCP59749 http://onsemi.com 7 typical characteristics at t j = +25 c, v in = v out(typ) + 0.3 v, v bias = 5 v, i out = 50 ma, v en = v in , c in = 1 f, c bias = 4.7 f, and c out = 10 f, unless otherwise noted. figure 15. current limit vs. (v bias ? v out ) v bias ? v out (v) 4.5 4.0 3.0 2.5 1.5 1.0 0.5 0 0 2.0 4.0 6.0 i cl , current limit (a) +125 c +25 c ? 40 c 2.0 3.5 5.0 1.0 3.0 5.0
NCP59749 http://onsemi.com 8 applications information the NCP59749 dual ? rail very low dropout voltage regulator is using nmos pass transistor for output voltage regulation from v in voltage. all the low current internal controll circuitry is powered from the v bias voltage. the use of an nmos pass transistor offers several advantages in applications. unlike a pmos topology devices, the output capacitor has reduced impact on loop stability. vin to vout operating voltage difference can be very low compared with standard pmos regulators in very low vin applications. the NCP59749 offers programmable smooth monotonic start-up. the controlled voltage rising limits the inrush current what is advantageous in applications with large capacitive loads. the v oltage controlled soft start timing is programmable by external css capacitor value. the enable (en) input is equipped with internal hysteresis and deglitch filter. open drain type power good (pg) output is available for vout monitoring and sequencing of other devices. NCP59749 is a adjustable linear regulator. the required output voltage can be adjusted by two external resistors. typical application schematics is shown in figure 16. figure 16. typical application schematics v out 0.8 1 r 1 r 2 NCP59749 dropout voltage because of two power supply inputs v in and v bias and one v out regulator output, there are two dropout voltages specified. the first, the v in dropout voltage is the voltage difference (v in ? v out ) when v out starts to decrease by percents specified in the electrical characteristics table. v bias is high enough, specific value is published in the electrical characteristics table. the second, v bias dropout voltage is the voltage difference (v bias ? v out ) when v in and v bias pins are joined together and v out starts to decrease. input and output capacitors the device is designed to be stable for all available types and values of output capacitors 2.2 f. the device is also stable with multiple capacitors in parallel, which can be of any type or value. in applications where no low input supplies impedance available (pcb inductance in v in and/or v bias inputs as example), the recommended c in and c bias value is 1 f or greater. ceramic or other low esr capacitors are recommended . for the best performance all the capacitors should be connected to the NCP59749 respective pins directly in the device pcb copper layer, not through vias having not negligible impedance. enable operation the enable pin will turn the regulator on or off. the threshold limits are covered in the electrical characteristics table in this data sheet. if the enable function is not to be used then the pin should be connected to v in or v bias . output noise when the NCP59749 device reaches the end of the soft ? start cycle, the soft start capacitor is switched to serve as a noise filtering capacitor. output voltage adjust the output voltage can be adjusted from 0.8 v to 3.6 v using resistors divider between the output and the fb input. recommended resistor values for frequently used voltages can be found in the table 6. programmable soft ? start the soft-start ramp time depends on the soft start charging current i ss, soft-start capacitor value c ss and internal reference voltage v ref . the soft ?start time can be calculated using following equations: t ss = c ss x (v ref / i ss ) [s, f,v,a] or in more practical units t ss = c ss x 0.8v / 0.44 = c ss x 1.82 where t ss = soft ? start time in miliseconds c ss = soft ? start capacitor value in nano farads capacitor values for frequently used soft-start times can be found in the table 7. the maximal recommended value of c ss capacitor is 15 nf. for higher c ss values the capacitor full discharging before new soft-start cycle is not guaranteed. current limitation the internal current limitation circuitry allows the device to supply the full nominal current and surges but protects the device against current overload or short. thermal protection internal thermal shutdown (tsd) circuitry is provided to protect the integrated circuit in the event that the maximum junction temperature is exceeded. when tsd activated , the regulator output turns off. when cooling down under the low temperature threshold, device output is activated again. this tsd feature is provided to prevent failures from accidental overheating.
NCP59749 http://onsemi.com 9 table 6. resistor values for programming the output voltage v out (v) r 1 (k ) r 2 (k ) 0.8 short open 0.9 0.619 4.99 1.0 1.13 4.53 1.05 1.37 4.33 1.1 1.87 4.99 1.2 2.49 4.99 1.5 4.12 4.75 1.8 3.57 2.87 2.5 3.57 1.69 3.3 3.57 1.15 note: v out = 0.8 x (1 + r 1 /r 2 ) resistors in the table are standard 1% types table 7. capacitor values for programming the soft ? start time soft ? start time c ss 0.2 ms open 0.5 ms 270 pf 1 ms 560 pf 5 ms 2.7 nf 10 ms 5.6 nf 18 ms 10 nf table 8. ordering information device output current output voltage junction temp. range package shipping NCP59749mn2adjtbg 3.0 a adj ? 40 c to +125 c qfn20 3000 / tape & reel
NCP59749 http://onsemi.com 10 package dimensions qfn20 5x5, 0.65p case 485db issue o seating 0.15 c (a3) a a1 d2 b 1 11 16 e2 20x 6 l 20x bottom view detail a top view side view d a b e 0.15 c pin one reference 0.10 c 0.08 c c e notes: 1. dimensions and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters. 3. dimension b applies to plated terminal and is measured between 0.25 and 0.30 mm from the terminal tip. 4. coplanarity applies to the exposed pad as well as the terminals. 5. optional features. plane dim min max millimeters a 0.80 1.00 a1 ??? 0.05 a3 0.20 ref b 0.25 0.35 d 5.00 bsc d2 3.05 3.25 e 5.00 bsc e2 e 0.65 bsc l 0.45 0.65 3.05 3.25 *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* 0.65 3.30 0.40 3.30 20x 0.78 20x 5.30 5.30 l1 detail a l alternate terminal constructions l detail b alternate construction note 4 detail b note 3 l1 ??? 0.15 pitch dimensions: millimeters a m 0.10 b c m 0.05 c a m 0.10 b c package outline recommended a m 0.10 b c note 5 on semiconductor and are registered trademarks of semiconductor co mponents industries, llc (scillc). scillc owns the rights to a numb er of patents, trademarks, copyrights, trade secrets, and other intellectual property. a list ing of scillc?s product/patent coverage may be accessed at ww w.onsemi.com/site/pdf/patent ? marking.pdf. scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/ or specifications can and do vary in different applications and actual performance may vary over time. all operating parame ters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the right s of others. scillc products are not designed, intended, or a uthorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in whic h the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or us e scillc products for any such unintended or unauthorized appli cation, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unin tended or unauthorized use, even if such claim alleges that scil lc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyrig ht laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5817 ? 1050 NCP59749/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative
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